X86: Prefer TSC-deadline timer in Xen

X86: Prefer TSC-deadline timer in Xen

The new TSC Deadline Timer offers system software a low overhead
per-logical-thread deadline timer in TSC units.

The timer is implemented via a new architectural 64-bit register,
IA32_TSC_DEADLINE_MSR. Reads and writes of this MSR occur in program
order, but are non-serializing.

The support for this feature is indicated by
CPUID.01H:ECX.TSC_Deadline[bit 24] =3D 1 as documented in the Intel
Architecture Software Developer's Manual.

The LOCAL APIC on new processors has a mode where its underlying
hardware timer can now be accessed via the non-serializing
IA32_TSC_DEADLINE_MSR in TSC tick units.

If this mode is present, prefer it over the traditional LAPIC timer
mode.  KERN_DEBUG dmesg will print "TSC deadline timer enabled" when
TDT is used.

Bootparam "tdt=off" is available to revert to LAPIC timer mode.

This patch is based on original work by Len Brown for Linux kernel.

cc: Len Brown <len.brown@intel.com>
Signed-off-by: Wei Gang <gang.wei@intel.com>
Signed-off-by: Keir Fraser <keir@xen.org>